The present invention generally pertains to microelectronic memories and is particularly directed to an improvement in the storage cell structure of a dynamic metal-oxide-semiconductor (MOS) random access memory (RAM).
Referring to FIG. 1, a dynamic MOS RAM has a plurality of data lines 10 and selection lines 11 and a plurality of storage cells 12 connected thereto. The storage cells 12 are arranged in rows and columns that are connected to the respective data lines 10 and selection lines 11. To address a specific storage cell, signals must be provided on both the data line and the selection line that correspond to that cell. The shading of the cells in FIG. 1 depicts the storage cell in the sixth column corresponding to data line 10f and in the fourth row corresponding to selection line 11d being addressed in response to signals being placed on lines 10f and 11d.
A schematic circuit diagram of a storage cell of a dynamic MOS RAM is shown in FIG. 2. A charge on a given data line 10 representing a data bit is stored on the first plate 21 of a storage capacitor 22 when a field effect transistor (FET) 23 having its conduction terminals 24, 25 respectively connected to the data line 10 and the first plate 21, is gated by a signal on a given selection line 11. The second plate 27 of the storage capacitor 22 is connected to a reference potential terminal V.sub.DD. The conduction terminals 24, 25 of the FET 23 commonly are referred to as the source and the drain. In a dynamic MOS RAM storage cell the source and drain functions of the conduction terminals are interchangeable depending upon whether data is being stored in or retrieved from the storage cell. Data is retrieved from the cell by the charge stored on the first plate 21 being transferred to the data line 10 when the FET is gated by a signal on the selection line 11.
FIG. 3 is a cross-sectional view (not drawn to scale) of a typical prior art storage cell in a dynamic MOS RAM. The cell includes a semiconductor substrate 28. The first conduction terminal is a region in the substrate defined by a diffusion 29 of conductive material. The first conduction terminal is connected in common with one of the data lines. The second conduction terminal of the MOSFET is defined by a conductive layer 30 at the junction of the semiconductor substrate 28 and an insulating dielectric material 31 deposited thereon. The gate of the MOSFET is defined by a conductive layer 32. The first plate of the storage capacitor is defined by the conductive layer 30; and the second plate of the storage capacitor is defined by the conductive layer 33. The conductive layer 33 is separated from the conductive layer 30 by the insulating layer 31. The conductive layer 32 is separated from the conductive layer 33 and the substrate 28 by an insulating layer 34. Typically the conductive layer 30 is an inversion layer which is formed in a depletion region 35 that is created when the conductive layer 33 is biased with respect to the substrate 28. Alternatively the conductive layer 30 is an implanted layer in the substrate 28 that is formed in accordance with the teaching of pending U.S. patent application entitled "Semiconductor Capacitor Especially Useful In An Integrated Semiconductor Structure With An MOS Device Including Fabrication Methods Therefor", Ser. No. 788,872 filed Apr. 19, 1977 by the inventors herein together with Andrew G. Varadi. A gating signal applied to the conductive layer 32 enables charge to be transferred between the conductive region 29 and the conductive layer 30.
The prior art structure of FIG. 3 has certain disadvantages. The presence of the first plate 30 of the storage capacitor in the substrate 28 makes it necessary to dedicate at least a minimum portion of the substrate for providing isolation between the respective conductive layers 30 that define the first plates in adjacent cells. As a result the storage capacitor occupies only about 20% of the area in a single cell.
Also, there is significant leakage of charge from the first plate 30 of the storage capacitor through the depletion region 35 in the substrate 28.